Wireless transmitting/receiving apparatus and method

ABSTRACT

The present invention discloses a wireless transmitting/receiving apparatus for transmitting and receiving large amounts of digital data using a commercial wireless transmitting/receiving apparatus. The wireless transmitting apparatus includes a data converter for mapping multibit digital data by a data symbol in accordance with a predetermined mapping table, for converting the data symbol to an analog signal, and for outputting the analog signal, and a wireless transmitter for modulating the analog signal and for transmitting the signal wirelessly. The wireless receiving apparatus includes a wireless receiver for demodulating a wireless signal received to an analog signal, and a data restoration section for converting the analog signal to a digital signal in accordance with a predetermined mapping table, conducting an inverse symbol mapping on the digital signal, and outputting the digital signal.

TECHNICAL FIELD

[0001] The present invention relates to a wirelesstransmitting/receiving apparatus and method. In particular, the presentinvention relates to a wireless transmitting/receiving apparatus andmethod that can transmit and receive a large amount of digital datausing a commercial wireless transmitter/receiver.

BACKGROUND ART

[0002] It has been long since a wireless infrared transmitter/receiverwere commercialized. Now one can easily get the small-sizedtransmitter/receiver at a very low price. In contrast, atransmitter/receiver for transmitting and receiving a large amount ofdigital data is very complicated and expensive, and thus it has been aburden on the public to use in everyday life. Therefore, scientists'interest naturally turned to the development of an inexpensivetransmitting/receiving apparatus that can transmit and receive enormousdigital data wirelessly.

[0003] For example, a wall television receiver that adopts a displayelement such as a PDP (Plasma Display Panel) or LCD (Liquid CrystalDisplay) has been developed as a multimedia display apparatus.

[0004] However, the wall television receiver as the multimedia displayapparatus is not always convenient though. For one thing, when the walltelevision receiver is used for the multimedia display apparatus, aplurality of signal sources should be connected to the televisionreceiver by wire, which consequently limits not only the clearancebetween the wall television receiver and the plurality of sources, butalso the position for installing the television receiver. Besides, manylines for connecting the sources and the wall television receiverobviously spoils the beauty of the wall.

[0005] In order to solve the above-described problems, an infraredtransmitter/receiver that interfaces a wall television receiver and aplurality of sources by wireless has been adopted. The technologyemployed in this conventional infrared transmitting/receiving apparatusis not explained with reference to a block diagram shown in FIG. 1. Asdepicted in FIG. 1, the infrared transmitting/receiving apparatuslargely includes a transmitter 100 installed in the source, and areceiver 200 installed in the wall television receiver.

[0006] A modulator 102 in the transmitter 100 modulates AV(Audio andVideo) signals transmitted from a source, and prevents any type of crosswith other apparatuss using the infrared technology, such as a remotecontroller or a wireless headphone, etc. Also, the modulator 102 is veryuseful for minimizing noises generated due to the surroundingenvironment like sunwrite and fluorescent write, thereby improvingreception sensitivity. The modulated signals are then inputted in aluminous element driver 104, and the luminous element driver 104 drivesa luminous element 106, and generates an infrared optical signalcorresponding to the inputted signal. Here, as for the luminous element106, LED (Write Emit Diode), one of the typical optical transmittingelements, is widely used.

[0007] The infrared optical signal is received to a receiving element202 of the receiver 200. Typically used optical transmitting element forthe receiving element 202 is a photodiode. The receiving element 202provides an electric signal corresponding to the received infraredoptical signal to an amplifier 240. The amplifier 240 sends the signalprovided by the receiving element 202 to a demodulator 206. Thedemodulator 206 demodulates the amplified signal and provides it to thewall television receiver as the AV signals.

[0008] Based on the operation system as described above, theconventional infrared transmitter/receiver can interface the sourceswith the wall television receiver wirelessly, and in result, people donot have to be bothered so much with a place where to install the walltelevision receiver, not ruining the beauty of the wall at the sametime.

[0009] Moreover, anyone can freely install the conventional infraredtransmitting/receiving apparatus because the infrared optical signal isavailable to everyone and its use was not against the radio regulationat all. Further, although the optical signal can not pass through anobstacle, its short transmission distance is very effective to maintainthe security.

[0010] In the meantime, the conventional infrared transmitter/receiverhas been originally developed for the transmission of analog signals ofan NTSC (National Television System Committee) type. Accordingly, thetransmission band of the commercialized infrared transmitting/receivingapparatus is limited to below NTSC under the influence of the modulator,characteristics of the high output LED driver, the photo diode, and thedemodulator.

[0011] However, as more digital technologies are under the development,and most of multimedia signals including PC signals are digitalized, theinfrared transmitting/receiving apparatus is no longer attractive to theusers. Instead, a wireless transmitting/receiving apparatus that isinexpensive yet capable of transmitting and receiving a great amount ofdigital data needs to be developed more than ever.

DISCLOSURE OF THE INVENTION

[0012] It is, therefore, an object of the present invention to provide awireless transmitting/receiving apparatus and a method thereof, in orderto transmit and receive a large amount of digital data wirelessly usingan inexpensive wireless transmitting/receiving apparatus that hasalready been commercialized.

[0013] To achieve the above object, there is provided a wirelesstransmitting apparatus which includes a data converter for mappingmultibit digital data by a data symbol in accordance with apredetermined mapping table, converting the data symbol to an analogsignal, and outputting the analog signal; and a wireless transmitter formodulating the analog signal and transmitting the modulated signalwirelessly.

[0014] In another aspect of the present invention, there is provided awireless receiving apparatus which includes a wireless receiver forreceiving a wireless signal and for modulating the signal to an analogsignal; a data restoration section for converting the analog signal to adigital signal, inverse-symbol-mapping the digital signal onto digitaldata in accordance with a predetermined mapping table, and outputtingthe digital data.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above object, other features and advantages of the presentinvention will become more apparent from the following detaileddescription when taken in conjunction with the accompanying drawings, inwhich:

[0016]FIG. 1 is a block diagram illustrating a conventional wirelesstransmitting/receiving apparatus;

[0017]FIG. 2 is a view illustrating a data symbol format according to apreferred embodiment of the present invention;

[0018]FIG. 3 is a block diagram illustrating a wireless transmittingapparatus according to a first embodiment of the present invention;

[0019]FIG. 4 is a view illustrating a process of the wirelesstransmitting apparatus shown in FIG. 3;

[0020]FIG. 5 is a block diagram illustrating a wireless receivingapparatus according to the first embodiment of the present invention;

[0021]FIG. 6 is a view illustrating a process of the wireless receivingapparatus shown in FIG. 4;

[0022]FIG. 7 is a block diagram illustrating a wireless transmittingapparatus according to a second embodiment of the present invention;

[0023]FIG. 8 is a detail circuit diagram of a first randomizer of FIG.7;

[0024]FIG. 9 is a block diagram illustrating a wireless receivingapparatus according to the second embodiment of the present invention;and

[0025]FIG. 10 is a detail circuit diagram of a first derandomizer ofFIG. 9.

BEST MODE FOR CARRYING OUT THE INVENTION

[0026] Preferred embodiments of the present invention will now bedescribed with reference to the accompanying drawings. In the followingdescription, same drawing reference numerals are used for the sameelements even in different drawings. The matters defined in thedescription such as a detailed construction and elements of a circuitare nothing but the ones provided to assist in a comprehensiveunderstanding of the invention. Thus, it is apparent that the presentinvention can be carried out without those defined matters. Also,well-known functions or constructions are not described in detail sincethey would obscure the invention in unnecessary detail.

[0027] According to the present invention, it is possible to transmitand receive digital data through an inexpensive transmitting/receivingapparatus by converting the digital data to NTSC (National TelevisionSystem Committee) signal that is one of AV signals, using a commercialwireless transmitting/receiving apparatus. Furthermore, the presentinvention provides a method of mapping multibit digital data by a singledata symbol, thereby enabling to transmit large amounts of digital datathrough a limited transmission band.

[0028] The data segment, as shown in FIG. 2, includes a sync symbol anda data symbol. For instance, the data segment can include 10 syncsymbols and 100 data symbols. In such case, if a data segment weredesignated as 1[H], 1[H] would correspond to all the 110 symbols.Particularly, the sync symbol is obtained by symbolizing the sync signalfor extracting the data symbol, while the data symbol is obtained bymapping the multibit digital data. The data segment has a total of 16levels ranging from level 0 through level 15. The levels from 0 through5 are sync symbol levels, representing sync symbols, and the levels from6 through 13 are data symbol levels, representing valid data symbols.Therefore, the present invention differentiates the sync symbol levelsand the data symbol levels, which consequently makes it much easier toextract the sync symbols among others as well as to make the formationof the data segment be similar to the NTSC signal. Here, the level ofthe data segment can be 4-bit data (one of 0000 through 1111)

[0029] One of the data symbols conducts mapping 3-bit digital data. Inother words, the digital data from 000 through 111 are mapped to thedata symbols of level 6 through level 13, respectively. Accordingly, therate of the data symbol is one third of the rate of the digital data. Insuch manner, the preferred embodiment of the present inventionintroduced the 8-level mapping method for mapping 3-bit digital to asingle data symbol. However, if the user wishes to increase thetransmission rate, he can increase the bit number of digital data thatare mapped per data symbol. One thing to be aware when increasing thebit number of digital data that are mapped per data symbol, even thoughthe receiver might have the equivalent SNR (Signal to Noise Ratio), adecision level is relatively decreased, which consequently increases theerror percentage of the receiver. Therefore, the number of mappinglevels should be determined very carefully in consideration with thecharacteristic of the SNR of the transmitting/receiving channel.

[0030] Now the transmitting/receiving apparatus m accordance with thefirst preferred embodiment of the present invention is explained withreference to FIGS. 3 through 6.

[0031]FIG. 3 is a block diagram illustrating the transmitting/receivingapparatus according to the first preferred embodiment of the presentinvention. As shown in FIG. 3, a bit stream transmitted from the signalsource is inputted to a serial to parallel converter 302 in a dataconverter 300. The serial to parallel converter 302 converts the bitstream that has been inputted in serial according to a clock provided bya first clock divider 310 to 3-bit section, and output terminals the bitstream in parallel. The bit stream that is outputted in parallel on thesection of 3-bit is then inputted in a symbol mapper 306 in a symbolmapper 304. Here, the symbol mapper 306 conducts mapping of the 3-bitbit stream to a single data symbol with reference to a mapping table.The mapping table shows the digital data from 000 through 111 that aremapped to the data symbols from level 6 through level 13. A first FIFOsection 314, or a buffer, writes up the data symbols serially inaccordance with a write clock provided by the first clock divider 310,and reads the data symbols serially in accordance with a read clockbefore outputting the data symbols. As for the first FIFO section 314, adual async FIFO can be used. In the meantime, a first gate section 312starts to count the clock that has been inputted, and proceeds toprovide the read clock to the first FIFO 314 at the point where thecount value reaches a first fixed number. In the subject situation, ifthe count value reaches a second fixed number, the first clock gatesection 312 discontinues providing of the read clock and countingprocess, and starts to count again. In short, the first clock gatesection 312, providing that the whole data segment is 1[H], provides theread clock to the first FIFO section 314 during the period of the wholedata segment being occupied by the data symbols, while stops outputtingthe read clock during the period of the whole data segment beingoccupied by the sync symbols. That is to say, suppose that the datasegment is composed of a total of 110 symbols, i.e., 100 data symbolsand 10 sync symbols, the first clock gate section 312 outputs the readclock during the data symbol period according to an equation 1, whilediscontinues outputting the read clock during the sync symbol periodaccording to an equation 2 as follows:

Data Symbol Period=1[H]×(100/110)  EQ. (1)

Synchronous Symbol Period=1[H]×(10/110)  EQ. (2)

[0032] Accordingly, the first FIFO 314, according to the read clock,reads the data symbols only in a portion where the data symbols arelocated in the whole data segment, and provides the data symbols to amultiplexer 318. And, a sync generator 316 generates the sync symbolsmanifesting the synchronism of the data segment, and provides the syncsymbols to the multiplexer 318. Here, the multiplexer 318 generates asingle data segment by multiplexing the data symbols and the syncsymbols. The data segment generated in this way is then inputted in a DA(Digital to Analog) converter 320. The DA converter 320 converts theinputted data segment to analog signal, and provides it to a frequencymodulation section 322. The frequency modulation section 322 modulatesthe inputted analog signal to frequency, provides the frequency to adriver 324. The driver 324 operates a luminous element 326 in order togenerate a corresponding infrared signal (IR) to the modulated signal.Typically used elements for the conventional A/V infrared transmittercan be employed for the luminous element 326.

[0033] The operation of the wireless transmitting apparatus is nowexplained with reference to FIG. 4. The parallel data provided by theserial to parallel converter 302 is converted to the data symbol by thesymbol mapper 306. The data symbol is inputted in the multiplexer 318through the first FIFO section (314), and the multiplexer 318 generatesthe data segment by inserting the sync symbol of the first fixed numberto each data symbol of the second fixed number. The data segment is thenconverted to the analog signal through the DA converter 320, and isinputted in the frequency modulation section 322.

[0034] Referring to FIG. 5, the wireless receiving apparatus inaccordance with the first preferred embodiment of the present inventionis now explained.

[0035] A receiving element 400 receives the infrared signal (IR),converts it to an electric signal, and provides the electric signal tothe FM (Frequency Modulation) demodulator 402. The FM demodulator 402demodulates the inputted electric signal, and inputs the signal in theAD (Analog to Digital) converter 416 and a sync detector in a datarestoration section 404, respectively. Typically used elements for theconventional AN infrared transmitter can be employed for the luminouselement 326 as well.

[0036] The sync detector 406 detects a sync level interval of anoutputting signal of the FM demodulator 402, and generates acorresponding sync signal to provide it to a PLL (Phase Locked Loop)section 410 in a clock regenerator 408. The PLL section 410 generates astabilized reference clock in accordance with the sync signal, andprovides the reference clock to a second clock divider 412. Based on thereference clock, the second clock divider 412 generates a variety ofclocks and provides them to each section.

[0037] The AD converter 416 converts the analog signal provided by theFM demodulator 402 to the digital data, and outputs the digital dataaccording to the clock provided by the FM demodulator 402. Here, the ADconverter 416 outputs 4-bit digital data. The 4-bit digital data is thenprovided to a second FIFO section 420 in an inverse symbol mappingsection 418.

[0038] A second clock gate 414 detects the level of the receiving signalthrough the 4-bit digital data outputted by the AD converter 416. If thedetected level is one of the data symbol levels, the second clock gate414 provides a write clock from the second clock divider 412 to thesecond FIFO section 420. The second FIFO section 420, or the buffer,writes up the 4-bit digital data that have been provided by the ADconverter 410 in accordance with the write clock. The 4-bit digital databecomes the data symbol. In other words, among other data segmentsreceived, only the data symbol is saved in the second FIFO section 420.The data symbol saved into the second FIFO section 420 is then readaccording to the read clock of the second FIFO section 420 that isprovided by the second clock divider 412, and is provided to the inversesymbol mapper 422. Here, the read clock rate the second clock divider412 outputs is designated lower than the write clock rate. It is done soto compensate the more increase in the data symbols being read comparedwith the data symbols that are lit up, as the sync symbols included inthe data segment are eliminated.

[0039] The inverse symbol mapper 422 conducts an inverse symbol mappingof the data symbol provided by the second FIFO section 420 to a bitstream, and outputs the bit stream in parallel as 3-bit section. The bitstream outputted as 3-bit section is inputted in a parallel to serialconverter 424. The parallel to serial converter 424 converts theinputted 3-bit parallel bit stream to serial bit stream, and providesthe bit stream to the wall television receiver.

[0040] The operation of the wireless receiving apparatus is nowexplained with reference to FIG. 6. As shown in FIG. 6, the demodulatedsignal provided by the FM demodulator 402 is inputted in the ADconverter 416. The AD converter 426 converts the inputted signal todigital data, and provides the digital data to the second FIFO section420. At this time, the data outputted from the AD converter 416 is thedata segment including sync symbols and data symbols. Among othersymbols in the data segment, only the data symbols are saved in thesecond FIFO section 420 in the second clock gate section 414.Afterwards, the inverse symbol mapper 422 conducts the inverse symbolmapping of the data symbols saved in the second clock gate section 414,and outputs the data symbols as a bit stream of 3-bit section inparallel. Finally, the bit stream is saved in the parallel to serialconverter 424.

[0041] Another aspect of the present invention provides a wirelesstransmitting/receiving apparatus in accordance with a second preferredembodiment of the present invention, which is illustrated in FIGS. 7through 10.

[0042] The element and operation of the wireless transmitting/receivingapparatus according to the second preferred embodiment of the presentinvention is first explained with reference to FIG. 7. The bit streaminputted by the signal source is inputted in the serial to parallelconverter 502 in the data converter 500. The serial to parallelconverter 502 outputs the bit stream, inputted in serial according tothe clock (Fck) provided by a third clock divider 516, as 3-bit sectionin parallel. The bit stream outputted in parallel as 3-bit stream isinputted in a randomizer 504. The randomizer 504 randomizes the bitstream in order to prevent unstableness during DC coupling. Therandomizer 504 includes a first through a third randomizer (506 through510), each randomizer being connected to an output, respectively, in theserial to parallel converter 502 where three output terminals areavailable. Since the first through the third randomizers (506 through510) have the same constitution, only the first randomizer 506 isexplained with reference to FIG. 8.

[0043] The first randomizer 506 includes a first through a thirdexclusive OrGate (OXR1 through XOR3), and a first through a tenthD-FlipFlops (D1 through D10). The first randomizer 506 conducts therandomization process on the digital data based on the followingequations 3 and 4.

GI(X)=X ⁹ +X ⁴+1  EQ. (3)

G2(X)=X+1  EQ. (4)

[0044] The 3-bit bit stream that went through the randomization processof the randomizer 504 is inputted in the symbol mapper 514 in the symbolmapping section 512. The symbol mapper 514 conducts mapping of the 3-bitbit stream as a single data symbol with reference to the mapping table,and outputs the data symbol. A third FIFO section 522 writes up the datasymbol in consecutive order of the write clock (Fck/3) provided by thefirst clock divider 516, reads the data symbol in order of the readclock (n/m) (Fck/3), and then outputs the data symbol. The third clockgate section 520 starts to count the clock inputted, and proceeds toprovide the lead clock to the third FIFO section 522 at the point wherethe count value reaches the first fixed number. In the subjectsituation, if the count value reaches the second fixed number, the thirdclock gate section 520 discontinues providing of the read clock andcounting process, and starts to count again.

[0045] In short, according to the read clock, the third FIFO section 522reads the data symbols only in a portion where the data symbols arelocated out of the whole data segment, and provides the data symbols tothe multiplexer 526. And, the sync generator 524 generates sync symbolsand provides them to the multiplexer 526. The multiplexer 526multiplexes the data symbols and the sync symbols, and generates a datasegment using them. The data segment generated is inputted in a DA(Digital to Analog) converter 528. The DA converter 528 converts thedata segment to analog signal, and provides the analog signal to the FMdemodulator 530. Then, the analog signal undergoes the FM demodulationprocess by the FM demodulator 530, and is provided to a driver 532. Thedriver 532 drives the luminous element 534 to generate a correspondinginfrared signal (IR) to the modulated signal.

[0046]FIG. 9 is a block diagram illustrating the wireless receivingapparatus in accordance with the second preferred embodiment of thepresent invention.

[0047] The receiving element 600 receives the infrared signal, convertsthe infrared signal to the electric signal, and provides it the FMdemodulator 602. The FM demodulator 602 demodulates the inputtedelectric signal, and inputs the signal in the AD converter 616 and thesync detector 606 in the data restoration section 604. As for thereceiving element 600 and the FM demodulator 602, the elements of theconventional A/V infrared receiver can be employed.

[0048] The sync detector 606 detects the sync level interval of outputsignal of the FM demodulator 602, generates the corresponding syncsignal, and provides the sync signal to the PLL section 610 in the clockregenerator 608. The PLL section 610 generates a stabilized referenceclock (nFck) in accordance with the sync signal, and generates thereference clock to a fourth clock divider 612. The fourth clock divider612, based on the reference clock, generates a variety of clocks (e.g.,Fck, Fck/3, (n/m) Fck/3), and provides them to each section.

[0049] The AD converter 616 converts the analog signal provided by theFM demodulator 602 to digital data, and outputs the digital dataaccording to the clock provided by the fourth clock divider 612. Here,the AD converter 616 outputs the digital data as 4-bit data. The 4-bitdigital data is then provided to the inverse mapping section 618 and afourth FIFO section 620.

[0050] A fourth clock gate 614 provides the clock ((n/m Fck/3) as thewrite clock provided by the fourth clock divider 612 to the fourth FIFOsection 620, only when the sync detector 606 does not output the syncsignal. The fourth FIFO section 620 writes up the 4-bit digital dataprovided by the AD converter 610 in accordance with the write clock, andthe 4-bit digital data becomes the data symbol. That is, only the datasymbol among other data segment received is saved in the fourth FIFOsection 620. Then the data symbol saved in the fourth FIFO section 620is read according to the read clock (Fck/3) provided by the fourth clockdivider 612, and is provided to the inverse symbol mapper 622. Here, therate of the read clock (Fck/3) outputted by the second clock divider 412is designated to be lower than the rate of the write clock ((n/m)Fck/3).

[0051] The data symbol provided by the fourth FIFO section 620 undergoesthe inverse symbol mapping by the inverse symbol mapper 622, and theinverse symbol mapper 622 outputs the data symbol as 3-bit bit stream inparallel. The bit stream outputted in parallel as 3-bit is inputted in aderandomizer 624. The derandornizer 624 includes a first through a thirdderandomizers (626 through 630). Since the first through the thirdderandomizers (626 through 630) have the same constitution, only thefirst dirandomizer is explained here with reference to FIG. 10.

[0052] As shown in FIG. 10, the first derandomizer 626 includes a fourththrough a sixth exclusive OrGates (XOR4 through XOR6), and an elevenththrough a twentieth D-FlipFlops (D11 through D20). The firstderandomizer 626 performs the derandomization process on the digitaldata based on the following equations 5 and 6 below.

G2(X)=X+1  EQ. (5)

G1(X)=X ⁹ +X ⁴+1  EQ. (6)

[0053] The derandomized bit stream outputted is then inputted in theparallel to serial converter 632. The parallel to serial converter 632converts the inputted 3-bit parallel bit stream into a serial bitstream, and provides the serial bit stream to the wall televisionreceiver .

Industrial Applicability

[0054] In conclusion, the present invention is very economical anduseful because it employs a commercial and small sized and inexpensiveanalog wireless transmitting/receiving apparatus, in order to transmitand receive large amounts of digital data wirelessly.

[0055] While the invention has been described in conjunction withvarious embodiments, they are illustrative only. Accordingly, manyalternative, modifications and variations will be apparent to personsskilled in the art in write of the foregoing detailed description. Theforegoing description is intended to embrace all such alternatives andvariations falling with the spirit and.broad scope of the appendedclaims.

What is claimed is:
 1. A wireless transmitting apparatus, comprising: asymbol mapping section for converting multibit digital data to the datasymbol in accordance with a predetermined mapping table; a syncgenerator for generating a sync symbol; a multiplexer for generating adata segment by multiplexing the data symbol and the sync symbol; adigital-to-analog(DA) converter for converting the data segment to ananalog signal and outputting the analog signal; and a wirelesstransmitter for modulating the analog signal and transmitting themodulated signal.
 2. The apparatus of claim 1, wherein the symbolmapping section further comprises: a symbol mapper for converting themultibit digital data to the data symbol in accordance with the mappingtable; a buffer for writing, reading and providing the input data symbolto the multiplexer, for keeping the data symbol from being provided tothe multiplexer in an interval where the synchronous symbol out of thedata segment is to be inserted; a clock divider for providing to thebuffer a light clock for receiving and a serial to parallel converterfor outputting a bit stream received in parallel; a clock gate sectionfor providing a read clock to the buffer, the read clock reading thedata symbol lit up in the buffer and outputting the data symbol, and forkeeping the read clock from being provided to the buffer in an intervalwhere the sync symbol out of the data segment is to be inserted.
 3. Theapparatus of claim 2, further comprises a serial to parallel converterfor converting bit stream to the multibit digital data, providing themultibit data to the symbol mapping section.
 4. The apparatus of claim3, further comprising a randomizer connected between an output of theserial-to-parallel converter and the symbol mapping section, forrandomizing the multibit parallel data.
 5. The apparatus of claim 1,wherein the data segment includes at least one sync symbol and at leastone data symbol.
 6. The apparatus of claim 5, wherein a level of thesync symbol and a level of the data symbol are designated to bedifferent from each other.
 7. A wireless receiving apparatus,comprising: a wireless receiver for demodulating a received wirelesssignal received to an analog signal; and an analog to digital(AD)converter for converting the analog signal to a digital signal; aninverse symbol mapping section for inverse-symbol-mapping a digitalsignal outputted from the AD converter onto multibit digital data inaccordance with a predetermined mapping table, when a read clock isprovided; and a sync detector for extracting a sync signal from thedigital signal; a clock generating section for detecting data symbolregion based on the sync signal, and for generating the read clock whenthe data symbol region is detected.
 8. The apparatus of claim 7, furthercomprises a parallel to serial converter for converting the multibitdigital data outputted from the inverse symbol mapping section to aserial data and for outputting the data.
 9. The apparatus of claim 7,wherein the inverse symbol mapping section comprises: a buffer forbuffering a data symbol only among other digital signals received by theAD converter, an inverse symbol mapper for converting the data symbol tothe multibit digital data in accordance with the mapping table.
 10. Theapparatus of claim 7, wherein the clock gererating section comprises: aPLL section for generating a reference clock based on the synch signal;a clock divider for generating a write clock and a read clock to beprovided to the buffer by dividing the reference clock, and forproviding the read clock to the buffer; and a clock gate section forproviding the write clock received to the buffer when the sync detectordoes not detect a synch signal, and not providing the write clock to thebuffer when the sync detector detects a synch siganl.
 11. The apparatusof claim 7, wherein the clock generating section comprises: a PLLsection for generating a reference clock based on the synch signal; aclock divider for generating a write clock and a read clock to beprovided to the buffer by dividing the reference clock, and forproviding the read clock to the buffer; and a clock gate section forproviding the write clock received to the buffer when an output level ofthe Analog to Digital converter corresponds to a level of the datasymbol, and not providing the write clock to the buffer when the outputlevel of the Analog to Digital converter corresponds to a level of thesync symbol.
 12. The apparatus of claim 7, further comprises aderandomizer for derandomizing a multibit digital data outputted fromthe inverse symbol mapping section, being connected between the inversesymbol mapping section and the parallel to serial converter.
 13. Awireless transmitting method, comprising the steps of: (a) mapping amultibit digital data as a data symbol in accordance with apredetermined mapping table; (b) generating a sync symbol; (c)generating a data segment by multiplexing the data symbol and the syncsymbol; (d) converting the data segment to an analog signal andoutputting the analog signal; and (e) modulating the analog signal andtransmitting the modulated signal wirelessly.
 14. A wireless receivingmethod, comprising the steps of: (a) restoring an analog signal using awireless signal received; (b) converting the analog signal to a digitalsignal; (c) extracting a data symbol only among other digital signalreceived; and (d) converting the data symbol to a multi-bit digital datain accordance with a predetermined mapping table, and outputting themulti-bit digital.